Nils Affing
VHDL-based Design of a Superscalar RISC-V Processor with Reconfigurable Execution Units Targeting FPGAs

Abstract
In this thesis, we will showcase UOS-Core, a superscalar out-of-order RISC-V architecture following the RV32I ISA. With the base implementation provided by the department of computer engineering at the university of Osnabrück, the author extended this base implementation by a branch prediction component that utilizes components like Branch Target Buffer and Return Address Stack together with architecture related data structures to realize predictor that is capable of predicting branching patterns and restoring valid memory states in case of a missprediction within a single clock-cycle.
UOS-Core is developed directly for FPGA target technologies via extensive usage of global parameters that change configuration and the resource requirements of the architecture. The issue-width, as well as a variety of resource heavy memory components such as the Reorder-Buffer as well as the Branch Target Buffer can be parameterized to adjust the resource requirements to the desired target FPGA board. This reconfigurability is statically done and was a major part of this thesis besides the branch prediction aspect. With this approach, UOS-Core can be realized with under 20.000 LUTs while still obeying the RISC-V specifications. The upper bound for the resource consumption is not elaborated due to no limitations on the assignment of parameters, and therefore UOS-Core can theoretically be configured to utilize any arbitrary quantity of resources. With an intermediate resource heave configuration, we can show, that UOS-Core will approximately have speedup factors of 42% to 378% on unspecialized test programs in comparison to an optimal, hypothetical single-cycle implementation.
We want to emphasize, that UOS-Core is still under development and this thesis is representing the current state of the processor with the focus on branch prediction, static reconfigurability through parameters and general design concepts introduced.